Xác minh năng suất SRAM bao gồm các lỗi ngẫu nhiên và hiếm gặp
How GlobalFoundries used the Solido Design Environment’s AI-powered methodology to predict SRAM bit-fail counts.
Large disparities were observed between wafer level SRAM Access Disturb related bit-fails as measured on silicon wafers and the number of such bit-fails as predicted by intrinsic device variability alone. Root cause investigations pointed to a rare but random defect lowering threshold voltage of the NFET devices of the SRAM bit-cell. This work presents a novel method to enable the inclusion of such rare and random defects into yield prediction frameworks. Solido Design Environment (Solido DE) has been utilized to demonstrate that the bit-fail counts predicted using the proposed novel method match closely with the silicon data.
To read more, click here.
