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Nature Electronics volume 2, pages 307–312 (2019)
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The power density limits of complementary metal–oxide–semiconductor (CMOS) technology could be overcome by moving from a binary to a ternary logic system. However, ternary devices are typically based on multi-threshold voltage schemes, which make the development of power-scalable and mass-producible ternary device platforms challenging. Here we report a wafer-scale and energy-efficient ternary CMOS technology. Our approach is based on a single threshold voltage and relies on a third voltage state created using an off-state constant current that originates from quantum-mechanical band-to-band tunnelling. This constant current can be scaled down to a sub-picoampere level under a low applied voltage of 0.5 V. Analysis of a ternary CMOS inverter illustrates the variation tolerance of the third intermediate output voltage state, and its symmetric in–out voltage-transfer characteristics allow integrated circuits with ternary logic and memory latch-cell functions to be demonstrated.
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The data that support the plots within this paper and other findings of this study are available from the corresponding author on reasonable request.
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This work was supported by the Samsung Research Funding & Incubation Center of Samsung Electronics under project number SRFC-TA1703-07 and by the U-K Brand Research Fund (1.180037.01) of UNIST (Ulsan National Institute of Science & Technology). The authors are grateful to foundry support for 130-nm and 90-nm CMOS technology processes.
Center for Nanoelectronic Brain-inspired Systems, Department of Electrical Engineering, Ulsan National Institute of Science and Technology, Ulsan, Republic of Korea
Jae Won Jeong, Young-Eun Choi, Woo-Seok Kim, Jee-Ho Park, Sunmean Kim, Sunhae Shin, Kyuho Lee, Jiwon Chang, Seong-Jin Kim & Kyung Rok Kim
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K.R.K. conceived, planned and supervised the project. J.W.J. designed the layouts and foundry experiments, performed the device and circuit measurements and contributed to writing the initial draft of the manuscript. Y.-E.C. and W.-S.K. contributed to the measurements and simulations for experimental design. J.-H.P. and S.K. contributed to the circuit layout design. S.S. contributed to the initial design of the first foundry experiments and layouts. J.C. contributed to the device design, modelling and simulations. K.L. and S.-J.K. contributed to the circuit design and measurements. All authors discussed the results and wrote the manuscript.
Correspondence to Kyung Rok Kim.
The authors declare no competing interests.
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Supplementary Figs. 1–7 and Supplementary Table 1.
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Jeong, J.W., Choi, YE., Kim, WS. et al. Tunnelling-based ternary metal–oxide–semiconductor technology. Nat Electron 2, 307–312 (2019). https://doi.org/10.1038/s41928-019-0272-8
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DOI: https://doi.org/10.1038/s41928-019-0272-8
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