Trình biên dịch FPGA nhúng mới tối đa hóa hiệu quả triển khai IP

When designing IP for system-on-chip (SoC) and application-specific integrated circuit (ASIC) implementations, IP designers strive for perfection. Optimal engineering often yields the smallest die area, thereby reducing both cost and power consumption while maximizing performance.

Similarly, when incorporating embedded FPGA (eFPGA) IP into a SoC, designers prioritize these critical factors. eFPGA IP is inherently scalable, enabling it to be tailored to each customer’s specific requirements. However, the necessary FPGA logic is not only determined by the programmed design, but also by the compiler and FPGA architecture used.

Embedded FPGA provides crucial flexibility, allowing SoCs to adapt to changing standards, protocols, customer requirements and post-quantum cryptography algorithms as well as enables software acceleration and deterministic processing. Flex Logix’s EFLX eFPGA architecture delivers excellent performance, power, and area (PPA) metrics. It features a familiar 6-input lookup table (LUT) along with a highly efficient, patented routing switch matrix. This switch matrix reduces the number of metal stack layers, enabling EFLX to meet the stringent requirements of edge IoT devices.

Recently Flex Logix announced the availability of eXpreso, its 2nd generation EFLX eFPGA compiler and successor to the first-generation compiler, EC1.0. eXpreso, which has been in development for years, is now shipping to alpha customers for evaluation. The new compiler delivers up to 1.5x higher frequency, 2x denser LUT packing and 10x faster compile times for all existing EFLX tile and arrays. Now IC designers can further reduce eFPGA IP implementation to levels never seen before.

Let’s explore a practical application example. Crypto Agility is a common application for eFPGA as hackers continuously find new ways to compromise devices and novel cryptography solutions rapidly emerge. To address this, security companies like Xiphera provide solutions, such as post-quantum cryptographic algorithms. Shown below is NIST-approved ML-KEM IP core. Flex Logix’s EC1.0 compiler integrated this algorithm into six EFLX 4K tiles. However, the eXpreso compiler not only compressed the design down to just four tiles – a 50% area savings – but also achieved an impressive 98% utilization rate, a key feature of this new compiler technology.

Fig. 1: Xiphera ML-KEM Post Quantum Cryptography IP Core on four EFLX 4K Tiles @ 98% Utilization.

Below are a few more examples that illustrate the capabilities of EFLX architecture combined with eXpreso. These real-world applications highlight not only area reduction but also performance improvement.

Fig. 2: JPEG Encode IP.

Fig. 3: 256 Point FFT.

Fig. 4: SHA-512 IP.

Fig. 5: Tate Pairing (Complex Elliptic Field Calculation).

These examples not only demonstrate the effectiveness of eXpreso but also highlight the updated visual interfaces that better align with commercial tools. A thorough examination was carried out using a test suite that included hundreds of designs subjected to regression tests with both compilers. The examination shows remarkable outcomes.

Feature	Average Improvement	Benefit
Compilation Time	Over 5x	Greatly saving engineering time between design iterations
Frequency Improvement	21%	Faster design performance. Also saving engineering time as it is much easier to close timing on faster designs
Area Reduction	15%	Reduces required die area, saving cost and static power

Fig. 6: eXpreso vs EC1.0.

Flex Logix is dedicated to pushing the boundaries of technology through constant improvement, directly benefiting our customers with industry-leading power, performance, and area (PPA). If you’re interested in testing your IP on our tools, we can perform the analysis for you, or you’re welcome to download an evaluation version. If interested or simply want to learn more about Flex Logix IP, contact us at [email protected] or visit our website https://flex-logix.com.

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