Tăng tốc xác minh chéo miền đặt lại bằng kỹ thuật phân tích dữ liệu

By Reetika and Sulabh Kumar Khare

As the complexity of integrated circuit (IC) designs continues to rise, the task of verifying these designs has become increasingly challenging. The pace of this growth is staggering, with design complexity doubling roughly every 20 months. This exponential increase places immense pressure on verification processes, which must keep up to ensure that these sophisticated designs function as intended.

In today’s verification landscape, EDA tools for clock domain crossing (CDC) detection are widely used to ensure design quality. More recently, reset domain crossing (RDC) validation has gained importance due to the rise of asynchronous resets, which require verification to ensure data stability across different reset domains. Data transfer between asynchronous reset domains can lead to metastability, similar to clock domain crossing issues. Metastability can cause unpredictable behavior, which might not be detected until late in the design process or, worse, after the design has been fabricated. This makes RDC validation crucial for ensuring that asynchronous data stability is maintained across different reset domains, thereby preventing potentially catastrophic design failures.

Challenges in RDC Verification

One of the major challenges in ASIC verification arises from the large volume of data generated by RDC verification tools that needs to be meticulously analyzed to identify and resolve potential issues. Current manual processes involve multiple design runs and iterations to identify and resolve RDC violations, affecting sign-off schedules.

Most RDC violations stem from common design or setup issues, such as asynchronous resets mistakenly placed in different domains. By applying advanced data analysis techniques, we can suggest constraints—such as stable signal declarations, reset orderings, and isolation signals—to narrow down RDC analysis results. This reduces the initial number of RDC violations, allowing verification engineers to focus on actual issues, which leads to early verification closure. The progressive application of supervised data processing and data analytics techniques helps in the acceleration of RDC verification closure by analyzing RDC results to recognize patterns and suggest setup related constraints.

RDC Verification Using Data Mining

In the complex world of ASIC design, ensuring robust RDC verification is critical to preventing metastability and other timing-related issues. Traditional methods often involve exhaustive manual analysis, which can be time-consuming, prone to errors, and may lead to overlooked design bugs, resulting in costly silicon re-spins. However, the application of advanced, supervised data processing and analytics techniques has the potential to revolutionize this process.

By leveraging these techniques, we can significantly accelerate the RDC verification process. These methods analyze large datasets generated during RDC verification runs to identify recurring patterns and common root causes of violations. Once these patterns are recognized, the system can automatically suggest setup-related constraints that address the underlying issues, reducing the number of reported violations and focusing the engineer’s attention on genuine problems.

For example, the data analytics system might detect that a significant portion of RDC violations stem from improperly grouped reset domains or perhaps missing ordering-constraints between asynchronous reset signals. By generating specific recommendations to address these issues—such as adjusting reset groupings or defining ordering constraints—the verification process becomes much more efficient.

Key Recommendations:

• Reset Ordering: Ensuring the receiver flop’s reset occurs before the transmitter’s reset can prevent metastability. On the other hand, without defined ordering constraints, tools may report multiple RDC violations for the same issue.
• Synchronous Reset Domains: RDC issues arise when the source and destination registers have asynchronous resets. Grouping resets in synchronous domains during set up can reduce false RDC violations.
• Directive Specifications: Specifying conditions like clock-off constraints or stable output states before reset activation can prevent unnecessary RDC violations.
• Stable Signals: Marking signals that cross asynchronous reset domains as stable can help the tool avoid flagging them as potential RDC issues.
• Isolation Signals: Using isolation signals to block metastability can refine the identification of genuine RDC problems.
• Safe RDCs with Non-Resettable Register (NRR): Paths involving NRRs may be safe if subsequent flops share the transmitter’s reset domain. Properly specifying depth can reduce false RDC reports.

 

Additional suggestions from data analysis models can further resolve complex RDC issues, especially involving NRRs. By implementing these initial constraints, the overall number of RDC violations can be significantly reduced, allowing users to focus on actual bugs.

To enhance the analysis process, users can prioritize high-impact suggestions. Presenting results in a clear, correlated manner through reports or a GUI helps quantify the effectiveness of recommendations before applying them to RDC analysis, ensuring efforts are focused on critical areas.

Refer to Fig. 1 for an overview of the RDC verification process using advanced data analysis methods:

1. Run RDC analysis with the design RTL and constraints.
2. Apply data analysis to generate additional constraints.
3. Re-run RDC analysis with the refined setup.
4. Review the results.

Fig.1: RDC Verification using Data Analysis Techniques. Source: Siemens EDA.

Results

In RDC design verification, design and verification engineers face a major challenge in fixing the most common RDC problems related to incorrect or missing constraints for reset ordering and reset grouping. Typically, there can be hundreds of unsynchronized RDC paths that have a common root cause. If we are able to get some initial information about possible common causes for a number of RDC violations, we will be able to quickly solve a lot of issues and hence save a lot of time and effort.

The application of advanced data analytic techniques results in a major reduction of RDC violations detected in a design. In a test case on five IP/subsystems, we found that by applying the constraints and suggestions mentioned in this article, the RDC verification closure time for the IP/subsystem designs was reduced from around ten days to less than four days, as up to 60% of violations on average were resolved (refer to Fig.2). The reduction in RDC violations demonstrates the efficacy of the data analysis features in analyzing the data and providing setup guidance without designer intervention.

Fig. 2: Reduction in RDC violations due to RDC data analysis.

Conclusion

The manual verification of RDC results takes a lot of time and effort, and there is a high probability that design bugs may be overlooked. Our proposed solution for RDC verification, involving the application of constraints suggested by advanced data analytic techniques, reduces the manual set up and review effort, improves quality of results, and avoids neglecting to specify constraints that reduce the number of reported RDC violations.

To learn more about how the application of advanced data analytic techniques results in a major reduction of unsynchronized RDC crossings detected in a design, kindly download our full paper Reset domain crossing design verification closure using advanced data analytics techniques.

—Sulab Kumar Khare is associate director for Quest Design Solutions at Siemens EDA.

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