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High-volume products get more than their fair share of attention in the semiconductor world, but most chips don’t fit into that category. While a few huge fabs and offshore assembly and test (OSAT) houses process enormous volumes of chips, small fabs and packaging lines serve for lower volumes, specialized technology, and prototyping.
“There are companies that run literally one lot of 25 wafers a quarter,” said Tim Brosnihan, executive director of the Fab Owners’ Alliance and the MEMS & Sensors Industry Group at SEMI. “There is still a very good market for those. The margins are higher for niche and custom parts.”
The overwhelming bulk of chips made today use standard CMOS logic and traditional packages. But many industries require services the big foundries and OSATs may not be willing to provide. Demand remains strong for such services, however. These typically target specialized high-margin products, and some — but not all — require special processing. That keeps smaller manufacturers viable.
Not everyone requires high volume
Microprocessors, graphics processing units (GPUs), smartphone application processors, and memories go flying out the door by the hundreds of millions of units. All eyes are on them, because they account for the bulk of shipments. But they represent a small portion of the engineering activity, developing all manner of other chips that ship in modest volumes.
This is evident in military and aerospace (mil/aero) systems, which consumes low volumes of chips. “The defense industry uses a lot of specialty semiconductors, and it’s very small volumes,” said Brosnihan. Mil/aero is unusual in that it drives a number of long-term and sometimes leading-edge technology roadmaps through the Defense Advanced Research Projects Agency (DARPA), but this sector remains conservative in the technology it employs to ensure reliability and availability.
Many other technologies ship in lower volumes, as well. “There are optoelectronics and compound-semiconductor manufacturers, which don’t have to push the volumes that some of the some of our other larger companies will,” said Ryan Zrno, CEO at JST.
And while wearables such as fitness trackers need to be reliable enough, those that require FDA-approval and can truly claim to perform accurate diagnostics or treat disease ship in much smaller volumes. The key is sufficient margin for the finished product, and the packaging process often can be the element that creates the value.
“There are industries where the actual device itself is worth a lot more than the BOM (bill of materials),” said Dave Fromm, COO at Promex Industries. “If I’m making an implantable medical device, I might have 10 cents worth of components inside it. But the device is intrinsically worth a lot because it needs to work, and it needs to have the reliability to ensure that it does what it’s supposed to do, whenever you want it to.”
Most sensors are not sold in high volumes, with some notable exceptions. “Microphones in cell phones sell like a billion units yearly,” said Brosnihan. “But there are so many more that are made in much smaller volumes.” Inertial measurement units (IMUs), a combination of accelerometer and gyroscopes, also populate phones. The rest tend to serve in more specialized equipment such as industrial machines.
Navigation-grade IMUs, for example, are far more expensive than consumer-grade, but they’re also accurate enough for precise navigation, rather than just approximate. “Navigation-grade [IMUs] are definitely much lower volume and run out of smaller fabs,” Brosnihan said.
Fig. 1: Promex SMT assembly. Source: Promex
Other low-volume technologies include photonics and power electronics. There is one market, however, that surprisingly tends not to account for much low-volume silicon — universities and R&D labs. Although equipment makers may sell some low-volume equipment to them, the volumes are miniscule (and, of course, those customers don’t ship silicon for revenue).
Volume and mix
High volumes tend to grant access to the most advanced silicon processing technology. While this impacts the kinds of equipment and processing available, there’s one more fundamental controlling parameter — wafer size. Most equipment for mainstream high-volume markets fabricates chips on 300mm wafers. Their benefit is the huge number of chips yielding from a single wafer, reducing the number of wafers and lots to be processed for the same output.
Such wafers can be overkill for some applications, however. A 300mm wafer has more than double the area of a 200mm wafer, and production can be easier to plan with a steadier stream of smaller wafers instead of a bursty schedule of big ones. But most production learning results from high-volume production on 300mm wafers, so that learning is now benefitting 200mm. A lot of the advanced technology that’s been added to 300mm equipment has been back-ported to 200mm equipment.
“Volume” also can have nuances when considered along with product mix. “Texas Instruments in particular runs a high mix of products which add together to very high volumes, but any particular amplifier is probably lower volume,” said Brosnihan. As long as most of those chips share similar processing, they can be made cost-effectively.
Some companies, such as Analog Devices, are willing to split production between their own specialized lines and commercial foundries. When the device involves mainstream technology, the company outsources it. “If you look at Analog Devices, which is well known for small volume and high mix, a big chunk of their business is now outsourced to foundries like TSMC,” said Brosnihan. “They keep the more specialty stuff in-house.”
That provides Analog Devices with more flexibility for the mainstream parts, sidestepping the need to build a fab and then keep it full.
The high-volume chipmakers may still perform some lower-volume projects selectively. “I believe that TSMC probably runs some products at 100 wafers a month,” said Brosnihan. “I’m not going to say they’re interested in any 100-wafer opportunity that comes their way, but they will pick and choose ones that maybe over a few years could ramp up to volumes of thousands of wafers a month.”
Prototypes as low-volume archetypes
Packaging is experiencing more new configurations than silicon processing. Specialized devices increasingly are co-packaging multiple chiplets, as well as mechanical and optical elements. Such projects tend to be much more individually designed than a silicon chip. Some processes refined during those projects may become useful in higher volumes in the future, while others may be project-specific. “The majority of our revenue is based on production,” said Promex’s Fromm. “However, if you looked at the number of activities going on, the majority involves developing new processes.”
The prototyping phase, by definition, precedes production, and so volumes don’t reflect how a product eventually may ship. For packaging, pilot lines can develop and refine processes that can then be transferred to high-volume OSATs if the product ends up shipping more than a small line can support.
Such lines must be capable of a wide variety of processes. “We define heterogeneous integration as combining electronic and non-electronic parts within the package,” said Fromm. That includes “mechanical sawing and grinding these devices to make them very thin,” he said. “We can dice and grind other materials that are not silicon. Optical filters might be made out of quartz, glass, or sapphire. We dice ceramic materials and things like that. We can also cut all of the substrates to interposer size. And then, in terms of attachment, we have lots of methods for solder or adhesive attachment, joining small parts, connecting things mechanically, electrically, or thermally, or some combination thereof. And we have encapsulation methods to protect those things.”
Silicon R&D tends not to follow that “prototype here, production there” model for the most part. “It’s pretty common for [foundries] to have an R&D line to get cutting-edge technology to local customers quickly for qualification and to make sure they’re on target for those top-tier customers,” said Samer Bahou, director of marketing communications at SEMI. Brosnihan agreed: “I recently did a survey of fab owners to find out how many did research and development in their production line. And it was almost everybody.”
Foundries tend to limit these lines to some specific new step being evaluated, however. That allows them to do the rest of the processing on the standard production lines. The reason is that any change of equipment necessitates a re-qualification of a chip. Once it’s qualified in low volume, you want to be able to move directly into high-volume production using the exact same equipment.
Mixing R&D with production raises the age-old problem of production managers reluctantly ceding time to engineering. “There are better systems now for how many lots in the fab you allocate to engineering and R&D and what kind of priorities they’re given,” said Brosnihan. “Typically, the R&D team is given one hot lot. Everything else is thrown on standard queue times.”
Multi-project wafers (MPW) are often employed for silicon chip prototypes, allowing multiple companies to share wafers. This is an option only for chip and IP prototypes, however. They’re not suitable for low-volume production because scheduling and mix issues would be unmanageable. If one company’s chip grew in volume faster than another’s, then the latter would see a huge buildup of inventory resulting from the wafers required for the former.
Handling low-volume wafer production
Low production volumes tend to fall into one of two camps — new-product introductions (NPI), and products that will simply never ship in high volumes. For NPIs, a company may build a small number of units for samples, and to have on hand for early design, testing and reliability evaluations. For mainstream products, some companies may stock all their distributors with inventory, so the initial build may be substantial. Other companies build devices conservatively as orders come in.
NPI lots almost always are built in the same fab as the higher follow-on volumes for the re-qualification reasons mentioned above. One pair of Canadian companies has a unique model, however. A small firm called C2MI (Centre de Collaboration MiQro Innovation) handles prototyping and low-volume production. If volumes ramp beyond what it can manage, production transfers to Teledyne Dalsa, which intentionally keeps its equipment as close as possible to that used at C2MI to alleviate the requalification burden. These aren’t separate arms of one large company. “They are independent organizations that have a partnership,” said Brosnihan.
Lower volumes also affect equipment. Larger fabs want equipment that lets them build as much as possible as fast as possible. For many steps, that means as many wafers — hence, chambers on a machine — as possible. Small fabs need that same equipment, but less of it. “You have some of the bigger players that are just focused on larger companies,” said Zrno. “Yet these smaller compound-semiconductor manufacturers need a precision single-wafer system, and they’re not going to buy a 24-chamber tool.” This gives smaller equipment makers a market that the bigger ones might not target.
Unfortunately, geopolitics also affects decisions on where things can be built. Chips used in military and defense applications are typically built locally by a trusted contractor. The tradeoff is that local fabs and assembly houses tend to be more expensive.
Specialized processing, specialized fabs
Mainstream foundries are ill-suited for unusual technologies such as photonics and microelectromechanical systems (MEMS). The former involves both silicon and packaging. Lasers require compound semiconductors, and those lasers may then be affixed to a silicon chip or co-packaged with them. “These photonic circuits will introduce external optical fibers and V-grooves,” added Fromm, to hold the fibers reliably with positioning and angles that transfer light efficiently into and out of a fiber.
Silicon photonics can take advantage of any silicon process, but critical dimensions tend to be measured in microns, not in nanometers. So the tightest, most expensive processes aren’t necessary. Legacy processes are more cost-effective, and 200mm wafers typically serve the lower volumes of such chips well.
Some silicon processes, such as those used for MEMS, are notorious for requiring a new or modified process for each design. MEMS production tends to be dominated by names very different from TSMC (although TSMC does do some low-volume MEMS work). “Infineon would be the biggest MEMS microphone transducer supplier,” said Brosnihan. “Bosch makes more MEMS devices than TSMC.” STMicroelectronics ships a wide mix of MEMS sensors that together add up to significant volume. For other opportunities, designers can turn to specialized MEMS fabs such as Rogue Valley Microdevices.
High-end silicon features and low volumes are a fraught combination
Small fabs can acquire the necessary equipment for the processes they manufacture as long as the process isn’t too advanced. Although some equipment-makers explicitly make smaller, lower-volume versions of the equipment found in mainstream foundries, there’s a limit as processes advance, making equipment more expensive.
The poster-child for expensive equipment has to be the extreme-ultraviolet (EUV) lithography steppers from ASML, which can cost as much as $200 million each. Small fabs are never going to be able to afford such a capital outlay. That means the most advanced silicon nodes will remain forever inaccessible to small fabs. And it would seem to suggest that great ideas requiring advanced silicon, but shipping in low volumes, will never be feasible because anything at the high end would have to ship in high volume or not at all. But that’s not the case.
Wafer coring has emerged as a way around this limitation for products with sufficient margin. It’s not unusual for a specialized chip to consist mostly of standard processing followed by a smaller number of specialized layers atop the standard ones. A typical reason for doing this would be to “functionalize” the chip by adding different materials with special properties.
Because the bottom layers are standard, they can be built on any process that a foundry can handle, given sufficient volume. The catch is that they’ll typically be on 300mm wafers. The follow-on steps will typically happen in machines that work only with 200mm wafers. So the standard 300mm wafers are “cored.”
“There are companies that will buy 300mm high-density CMOS wafers, core them down to a 200mm wafer, and then run that wafer through some process that adds stuff on top for optics, sensors, optical, or biology,” said Brosnihan. The process is expensive and wasteful, but it works. “They throw half of the silicon away when they do a coring operation, so you better be making a huge margin.”
But for suitable opportunities, that approach provides access to both leading-edge and specialized processing.
Packaging is experiencing far greater process variety
The challenges encountered by packaging houses are growing, given how advanced packaging is evolving. Assembling multiple chiplets in a package is no longer leading edge, even if it does remain expensive compared with standard packages. But many projects involve further challenges. And with this class of product, processes haven’t yet stabilized into something standard.
“Is there a recipe that you can dial in and then run a class of devices,” asked Fromm. “In terms of processes and quality of input materials, adhesives, and other interconnection materials, that can come with maturity. A lot of the devices that we build are specific enough that each one will require an almost-from-scratch process.”
New materials are constantly in development, not just for silicon, but for packaging. One of the major challenges becomes bonding different materials together in a manner that’s stable and reliable as temperatures change. Each material has a coefficient of thermal expansion (CTE) that describes how much the material expands and contracts with changes of temperature.
“When you process these devices, to reflow solder or to cure adhesive, you’re changing temperature, and so you’re sensitive to the CTE mismatch between different materials,” Fromm said. “When you have only one or two materials, as in a traditional device, that’s pretty easy to manage. It’s more difficult when you have three, four, or five different materials that all have different CTEs. The CTE of silicon and that of an organic adhesive differ by a factor of 10 or 20. The path length becomes a bigger problem. You’re very sensitive to warpage across a longer lever arm. These are disastrous problems. You break the parts, or you create reliability issues where the parts leave the factory and then fail early because they have latent failures due to stress and mechanical strain.”
Other challenges with new packaging approaches include co-planarity, given the number of solder balls that must connect reliably on a PCB or other panel. Some packages require windows to admit light, or they may have ports for gases or fluids. “With a lot of these devices for medical biotech, you need to have some kind of air cavity or open window of some sort,” said Rosie Medina, vice president of sales and marketing at Promex.
Medical packaging tends to be very specialized, especially for sensors that will enter someone’s body either through implantation or by having a patient ingest it. Those materials must be bio-compatible and hermetically sealed to protect the electronics from the harsh environment, and vice versa.
“If it’s part of an endoscope, there’ll be a business end that gets welded into something else,” explained Fromm. “And then, if we have implantables where the housing is a special bio-safe epoxy or adhesive or some sort of material that’s safe to be inserted into the body for some amount of time, in that case the housing itself is an encapsulant.”
NPI for packaging is more forgiving than it is for silicon. It’s not uncommon for sample quantities to be built onshore for quicker turnaround. The qualification implications are less dire than they are for wafers. “We’re doing quick turns,” explained Medina. “Customers might send one wafer off to our production division, and the balance of the 25‑wafer lot goes offshore. As soon as they get 25 samples, they can tell the other guys, ‘Yes, this is a good way to build them. We’ve tested them locally.’ Some customers may be selling IP, so we’re building multiple iterations of test vehicles or assembly lots, a couple hundred units at a time so that they can validate that it does what it’s supposed to do.”
Some products may remain onshore even in higher volumes. “We’ve seen medical devices where, even at high volumes, they still might not go offshore because it’s not worth bringing up, qualifying, and validating a new source,” noted Fromm.
But completing a new packaging evaluation can be inefficient and time-consuming. Different steps occur in different locations, requiring multiple transfers of the devices. “It’s better to have a one-stop solution, but there is no good advanced packaging lab in the U.S.,” said Hidenori Abe, executive director of the electronics business headquarters at Resonac. “We have a learning pipeline. Although we are a materials supplier, we need that line to test our material before proposing it to our customers. We are also running a consortium in Japan to try different equipment and material capabilities, and we want to bring that model to the U.S.”
Many forces keep the small suppliers alive
While the major foundries and OSATs have nothing to fear from small specialty houses, those smaller-scale manufacturers are thriving on projects the big chipmakers and OSATs cannot or will not take on. Whether it’s due to special processing needs, low anticipated production volume, complicated packaging, or sensitive politics, small fabs and packaging lines are finding lots of customers.
One can think of the marketplace as an orchard. The high-volume chipmakers and assembly firms can come through with automation that strips the easy-to-harvest fruit from the trees in high volumes and with high efficiency. But they can never get everything. So other companies can come in with specialty people and ladders to access the still-perfectly-good fruit left behind. As long as demand remains for all the fruit, both types of company can do well.
It seems unlikely that situation will change. In fact, given that advanced silicon processing is moving so far ahead and devices are becoming more customized, the demand for lower-volume manufacturing may rise. Just as is the case with burgeoning legacy silicon nodes, the unsung specialty houses are likely to continue thriving for a good long time.
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