Sử dụng mô hình khuếch tán để tạo vị trí chip (UC Berkeley)

A technical paper titled “Chip Placement with Diffusion” was published by researchers at UC Berkeley.

Abstract:

“Macro placement is a vital step in digital circuit design that defines the physical location of large collections of components, known as macros, on a 2-dimensional chip. The physical layout obtained during placement determines key performance metrics of the chip, such as power consumption, area, and performance. Existing learning-based methods typically fall short because of their reliance on reinforcement learning, which is slow and limits the flexibility of the agent by casting placement as a sequential process. Instead, we use a powerful diffusion model to place all components simultaneously. To enable such models to train at scale, we propose a novel architecture for the denoising model, as well as an algorithm to generate large synthetic datasets for pre-training. We empirically show that our model can tackle the placement task, and achieve competitive performance on placement benchmarks compared to state-of-the-art methods.”

Find the technical paper here. Published July 2024 (preprint).

Lee, Vint, Chun Deng, Leena Elzeiny, Pieter Abbeel, and John Wawrzynek. “Chip Placement with Diffusion.” arXiv preprint arXiv:2407.12282 (2024).

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