Nền tảng đóng gói FCBGA đúc mới cho các ứng dụng ô tô có độ tin cậy cao

The conventional flip chip ball grid array (FCBGA) package platform has wide industry usage and provides high electrical performance. However, as high performance requirements increased, it encounters significant challenges. FCBGA packages frequently encounter underfill cracks after long term reliability or harsh reliability test conditions for automotive devices. Figure 1 shows the typical underfill crack after a 175°C high temperature storage (HTS) test. And underfill crack is one of the critical failures that could lead to electrical and function failures.

Fig. 1: Typical underfill crack from conventional FCBGA.

Bump cracking is also one of the challenges for conventional FCBGA under temperature cycling (TC) stress testing to meet automotive qualification requirements. Typical bump crack aspects are fatigue of under-bump metallization (UBM) [4], cracking of the dielectric around the UBM [5] and intermetallic compound (IMC) failure of the bump [6,7]. Cracking of the dielectric under the UBM [8] is also a challenging issue for long term reliability test conditions for conventional FCBGA designs.

Another challenge for the conventional FCBGA is package warpage for large body sizes. As the requirements for performance increase, the package body size also increase and it leads to the potential for high package warpage. High package warpage is one of the root causes of board mounting failures.

The molded FCBGA platform has been developed to overcome the challenges of the conventional FCBGA [9]. This platform was designed to achieve a cost reduction and higher reliability performance [10] and to prevent underfill oxidation and cracking that occurred in the commercial FCBGA [11]. This means that the molded FCBGA has a strong potential for automotive devices with high reliability performance and stable stress characteristics of the bump and underfill areas. For large body FCBGAs, the molded FCBGA could be the solution to overcome high package warpage.

A previous simulation study confirmed that an mFCBGA design showed improved package warpage and lower bump and underfill stress compared to the FCBGA design. Figure 2 shows the package warpage simulation results for bare die cases. Case 1a shows a significant reduction in room temperature warpage which can be a great advantage for an FCBGA type package. Furthermore, if a molding compound material with different thermomechanical properties is carefully chosen, then both room temperature and high temperature warpage can be reduced as in case 1b. The lidded package type exhibits similar trends in terms of warpage behavior as shown in figure 3.

Fig. 2: Package warpage simulation results for Bare Die Cases.

Fig. 3: Package warpage simulation results for Lidded Cases.

Another simulation study involved normalized stress for bump and back end of line (BEOL) areas. Figure 4 shows that another important benefit is the ability to reduce the bump and BEOL layer stress. For bare die packages with and without a stiffener ring, simulation results indicated 7.7% lower bump stress in case of 0b and 0c. The same results from the lidded case as well the mFCBGA design were confirmed with reduced bump and BEOL stress of about 17.0% compared to the conventional FCBGA design as shown in figure 5.

Fig. 4: Bump & BEOL stress simulation results for Bare Die Cases.

Fig. 5: Bump & BEOL stress simulation results for Lidded Cases.

The final simulation involves the thermal interface material (TIM) strain comparison between the conventional FCBGA and the molded FCBGA packages. Figure 6 shows the representative 3D image for the simulation modeling.

Fig. 6: (a) Tensile Strain on the corner at Room Temperature, (b) Compressive Strain on the corner at Reflow Temperature, (c) Compressive Strain on the center at Room Temperature, and (d) Tensile Strain on the center at Reflow Temperature.

Simulations confirmed that the mFCBGA design can reduce the TIM elastic strain for maximum tension, compression at room temperature and maximum compression at high temperature cases (see Figure 7 Case 3a and 3b compared to Case 0a).

Fig. 7: TIM Strain Comparison by package design.

The simulation results confirmed that the molded FCBGA has advantages for automotive devices with reduced bump stress and for large body packages with lower package warpage. The epoxy molding compound’s (EMC’s) material properties are important parameters to determine the molded FCBGA package characteristics. After selecting the EMC material, the focus was on optimizing the overall process parameters of the mFCBGA. Various process and material-related factors can affect the warpage, molding process yield, quality and reliability [9]. However, seven different EMC materials, module to module (M2M) spacing and over mold thicknesses were evaluated to improve reliability performance, package and carrier warpage.

Experiment and result

EMC categorization

The purpose of the first experiment is to select the optimal EMC to make no bump, no underfill cracking and a flat package with carrier warpage under 1.00 mm. Prior to the experiments, new EMC materials were proposed. Seven EMC candidates were suggested with the properties of each provided by the technical data sheets. Table 1 shows the material properties of the 7 EMC candidates for the first trial DOE.

Table 1: The properties of 7 EMC candidates.

The new EMCs were categorized with mechanical properties based on their technical sheet data with a JMP tool. Current level analysis was evaluated through the contour and prediction profiler. The statistical methods used Hierarchical cluster, K means and principal component analysis (PCA). Figure 8 shows the Hierarchical cluster analysis result with the Ward method. This dendrogram indicates that if seven candidates are to be divided into four groups, they should be divided into 1, 2, 3 and the rest. Therefore, three EMCs with the most different characteristics were selected. Top priority EMCs are Leg2, Leg3 and Leg6.

Fig. 8: Hierarchical cluster analysis with Ward method.

Carrier warpage simulation

Based on the EMC categorization results, carrier warpage simulation proceeded with the 7 EMC materials from Table 1. Simulation results are shown in figure 9 with the blue bar chart being the carrier warpage simulation results. According to simulation results, the Leg2 & 4 could be the best options to reduce the carrier warpage. Leg1 POR shows ‘crying’ shape of carrier warpage mod, while the other legs show a ‘smiling’ shape. This occurs because the POR EMC material had a lower α1 CTE value than the other legs.

Four EMCs were selected by considering the top-priorities classified from statistical analysis and simulation results. The orange bar chart from figure 9 shows the actual carrier warpage after the mold process. However, there are some gaps between the simulations and actual values. The simulation results showed that a flat warpage could be detected at Leg2 and Leg4 EMCs but those actual values do not match the expected results (refer to the red arrows).

Fig. 9: Carrier warpage from simulations versus actual values.

Due to polymeric printed circuit board (PCB) components, the simulation formula cannot be applied to the molded platform and warpage modeling does not reflect the mold shrinkage factor in granular type form. It is suspected that it is only possible to apply mechanical properties to simulation modeling.

EMC and mold process evaluation

After measuring the actual warpage data, the mold warpage level is currently far from the ideal line (mold warpage=0). The JMP tool was used to analyze which properties of the EMC are important factors to reduce carrier warpage. Contour and prediction profilers showed that the EMC should be changed in the “Low CTE” direction. Figure 10 shows that if a low CTE EMC material is used, the carrier warpage will be ideal – flat. To achieve a low CTE for the EMC, adding Si fillers into the EMC aggregation is recommended.

Fig. 10: Contour profile for current EMC position.

Based on the simulation results, a new EMC which has low CTE parameter was proposed. The EMC requirements are CTE α1 8 ppm and Modulus 15 GPa. One EMC with low CTE and shrinkage was proposed per supplier as shown in table 2.

Table 2: The properties of 7 EMC candidates including New EMC.

Finally, mold carrier warpage was validated with four EMC as shown in table 3. The results were -2.70 mm warpage at the new EMCs. This improved carrier warpage from 5.07 mm with a smile shape to -2.70 mm with a crying shape. The low CTE is effective to reduce molded carrier warpage.

Table 3: DOE matrix and carrier warpage.

Dramatic mold carrier warpage improvement was confirmed  at both Leg2-1 and Leg6-1 with low CTE and extremely low shrinkage. However, neither EMC meets the target carrier warpage of < 1.00 mm. Therefore, further 3-way DOE was conducted for carrier warpage improvement with a process point of view. X factors in DOE are “EMC material,” “M2M spacing” and “over-mold thickness.” The Y factor in the DOE is mold carrier warpage.

Figure 11 shows the summary results. The warpage target (< 1.00 mm) was achieved and two factors (M2M spacing and over mold thickness) were identified to enable the reduction of molded carrier warpage. As M2M spacing is reduced, warpage showed a crying warpage. As the over-mold thickness increased, the molded carrier showed less smile or crying warpage.

Fig. 11: Carrier warpage summary from Final DOE.

Package warpage improvement for 5,500 mm² body size

Previous simulation results that showed high thermal conductive EMC can reduce package warpage at molded FCBGA package compared to conventional FCBGA were validated experimentally. A large body package with 5,500 mm² area was used as test vehicle. Figure 12 shows a mFCBGA with a high thermal conductivity (7W) EMC can dramatically reduce the package room temperature warpage from 360μm to 201μm (about 42% improvement). Therefore, the molded FCBGA design is a great solution for a large body package with high package warpage.

Fig. 12: Package warpage comparison between large body FCBGA and large body molded FCBGA designs.

Reliability test

No Lidded Type for 1,225 mm² body size

The reliability assessment for new molded FCBGA platform proceeded with no lidded type for the automotive Grade 0 level high temperature storage (HTS) test. A 1,225 mm² body size package was used as the test vehicle with 100 units tested. It passed HTS 2,000 hours without open/short (OS) test failures (see figure 13). Even at the 175°C condition for scanning acoustic tomography (SAT) inspection after HTS 2,000 hours, no EMC delamination or voids were detected (see figure 14). The cross-sectional view also showed no underfill cracking or degradation for all reading points including after HTS 2,000 hours with both 150°C and 175°C conditions (see figure 15). After performing planer sectioning to observe the underfill fillet, no abnormalities were observed at the same reliability conditions (see figure 16). Cross section results for bump after HTS 2,000 hours detected IMC growth followed by bump degradation with IMC voids with 175°C conditions that were clean with 150°C conditions (see figure 17). There is an electrical open failure risk even though it passed OS test after HTS 2,000 hours.

Fig. 13: Grade 0 HTS reliability test summary.

Fig. 14: SAT inspection results after HTS 2,000 hours.

Fig. 15: Cross section results for underfill fillet.

Fig. 16: Planer section results for underfill fillet.

Fig. 17: Cross section results for bump.

Lidded Type for 1,225 mm² body size

A full reliability test for the new molded FCBGA platform was conducted on a lidded type design for automotive Grade 0 level. The 231 test units passed precon L3, highly accelerated stress test (HAST) 264 hours, temperature cycling condition H (TCH) 2,000 cycles and HTS 2,000 hours without OS test failures (see figure 18). Also, the qualification set passed SAT inspection. No TIM delaminations or voids were detected under the flat lid (see figure 19). The cross-sectional view showed no underfill cracking or degradation for all reading points (see figure 20). As a result of planer section for underfill fillet, no underfill discoloration or cracks were found during reliability test (see figure 21). After cross-sectioning for bumps, no bump degradation was found during reliability tests (see figure 22).

Fig. 18: Grade 0 full reliability test summary.

Fig. 19: SAT inspection results for TIM area.

Fig. 20: Cross section results for underfill fillet.

Fig. 21: Planer section results for underfill fillet.

Fig. 22: Cross section results for bump.

Conclusions

The new mFCBGA package achieved the carrier warpage target (< 1.00 mm). EMC material properties (CTE α1 and modulus) and process parameters (M2M spacing and over mold thickness) were identified to reduce molded carrier warpage. Also, by using optimized EMC material and process parameters, package warpage improved about 42% compared to conventional FCBGA design for large body package and passed automotive Grade 0 level reliability testing for small body package. Further findings include:

• Optimized mechanical properties of EMC material is CTE 1α 8 ppm and modulus 15 GPa. A guideline range is 7 ppm < CTE <10 ppm and 15 GPa < Modulus <35 GPa based on statical analysis and experimental results.
• Optimized process parameters were found for M2M spacing and over-mold thickness, respectively. Wide M2M spacing and thick over-mold thicknesses are preferred to improve carrier warpage based on statistical analysis and experimental results.
• High thermal conductivity EMCs for molded FCBGA design can lead to package room temperature warpage reduction of about 42% compared to conventional FCBGA design for 5,500 mm² large body package.
• No lidded type of molded FCBGA with 1,225 mm² body size was identified as a good approach to enable automotive Grade 0 for FCBGA based on electrical (OS) and mechanical (planar and cross section) validation. No underfill cracks were found. Instead, the bump degradation occurs faster than the underfill degradation after subjection to Grade 0 conditions.
• Lidded molded FCBGA with 1,225 mm² body size did not show any failure defects such as TIM delamination, bump degradation or underfill cracking after reliability testing. It endured the Grade 1 and Grade 0 reliability conditions.

References

1. JEDEC standard for highly accelerated temperature and humidity stress test (HAST), JEDEC Standard JESD22-A110E.01, May 2021.
2. JEDEC standard for temperature cycling (TC), JEDEC Standard JESD22-A104-B, July 2000.
3. JEDEC standard for high temperature storage life (HTS), JEDEC Standard JESD22-A103D, December 2010.
4. R. Alberti, R. E. Vaion, A. Mervic, and S. Testa, “Metal fatigue in copper pillar Flip Chip BGA: A refined acceleration model for the aluminium pad cracking failure mechanism,” Microelectronics Reliability, vol. 55, pp.1838-1842, 2015.
5. Y. Tian, X. Liu, J. Chow, Y. P. Wu, and S. K. Sitaraman, “Experimental evaluation of SnAgCu solder joint reliability in 100-μm pitch flip-chip assemblies,” Microelectronics Reliability, vol. 54, pp. 939-944, 2014.
6. Y. S. Lai, M. K. Shih, C. C. Lee, and T. H. Wang, “Structural design guideline to minimize extreme low- k delamination potential in 40 nm flip-chip packages,” Microelectronics Reliability, vol. 52, pp. 2851-2855, 2012.
7. L. Yang and J. B. Bernstein, “Failure rate estimation of known failure mechanisms of electronic packages,” Microelectronics Reliability, vol. 49, pp.1563-1572, 2009.
8. Xuanlong Chen, Ji Cheng, Huiwei Wu, Liyuan Liu, “Open Failure Mechanisms of FCBGA Package under Temperature Cycling Stress”, 2017 IEEE 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), IEEE, 04-07 July 2017.
9. Laurene Yip and Raghunandan Chaware, “Overmolded flip chip packaging solution for large die FPGA with 65nm low-k dielectrics”, 2007 12th International Symposium on Advanced Packaging Materials: Processes, Properties, and Interfaces, IEEE, 03-05 October 2007
10. Michael Lyakas, Corey Reichman, Miguel Jimarez, “Package Technology Selection of 28nm High Power FPGA with Pb-Free Solder Bumps: Flip Chip Molded BGA (FCMBGA) versus Traditional Flip Chip Bare Die Package”, 46th International Symposium on Microelectronics (IMAPS 2013), Sept. 30 – Oct. 3, 2013.
11. Pradeep Lall and Aathi Raja Ram Pandurangan, “Effect of Long-Term Isothermal Exposure on Chip/Underfill Interfacial Crack Growth Under Mode – I Fatigue Loading”, 2022 21st IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (iTherm), IEEE, 31 May 2022 – 03 June 2022

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