Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors – Nature.com

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Nature volume 479pages 310–316 (2011)
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For more than four decades, transistors have been shrinking exponentially in size, and therefore the number of transistors in a single microelectronic chip has been increasing exponentially. Such an increase in packing density was made possible by continually shrinking the metal–oxide–semiconductor field-effect transistor (MOSFET). In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue. Recently, however, a new generation of MOSFETs, called multigate transistors, has emerged, and this multigate geometry will allow the continuing enhancement of computer performance into the next decade.
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Armstrong, G. A., Davis, J. R. & Doyle A. Characterization of bipolar snapback and breakdown voltage in thin-film SOI transistors by two-dimensional simulation. IEEE Trans. Electron Devices 38, 328–336 (1991).
Article  ADS  Google Scholar 
Moselund, K. E. et al. Punch-through impact ionization MOSFET (PIMOS): from device principle to applications. Solid State Electron. 52, 1336–1344 (2008).
Article  CAS  ADS  Google Scholar 
Zhang, Q., Zhao, W. & Seabaugh, A. Low-subthreshold-swing tunnel transistors. IEEE Electron Device Lett. 27, 297–300 (2006).
Article  CAS  ADS  Google Scholar 
Afzalian, A., Colinge, J. P. & Flandre, D. Physics of gate modulated resonant tunneling (RT)-FETs: multi-barrier MOSFET for steep slope and high on-current. Solid State Electron. 59, 50–61 (2011).
Article  CAS  ADS  Google Scholar 
Salahuddin, S. & Datta, S. Use of negative capacitance to provide voltage amplification for low power nanoscale devices. Nano Lett. 8, 405–410 (2008).
Article  CAS  ADS  Google Scholar 
Moore, G. E. Cramming more components onto integrated circuits. Electronics 8, 114–117 (1965).
Google Scholar 
Dennard, R. H. et al. Design of ion-implanted MOSFET’s with very small physical dimensions. IEEE J. Solid-State Circuits 9, 256–268 (1974).
Article  ADS  Google Scholar 
Skotnicki, T. & Boeuf, T. How can high-mobility channel materials boost or degrade performance in advanced CMOS. Symp. VLSI Technol. 153–154 (IEEE, 2010).
Google Scholar 
Engström, O. et al. in Nanoscale CMOS: Innovative Materials, Modeling and Characterization (ed. Balestra, F.) Ch. 2 (Wiley-ISTE, 2010).
Google Scholar 
Grove, A. S. Physics and Technology of Semiconductor Devices Ch. 11 (Wiley, 1967).
Google Scholar 
Colinge, J. P. Multiple-gate SOI MOSFETs. Solid State Electron. 48, 897–905 (2004). This technical review paper provides a detailed comparison of the efficiency of channel control by the gate with single-gate, double-gate, tri-gate and gate-all-around configurations, and it introduces the concept of natural length and shows its relationship to short-channel effects.
Article  CAS  ADS  Google Scholar 
Skotnicki, T. et al. Innovative materials, devices, and CMOS technologies for low-power mobile multimedia. IEEE Trans. Electron Devices 55, 96–130 (2008).
Article  ADS  Google Scholar 
Sekigawa, T. & Hayashi, Y. Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate. Solid State Electron. 27, 827–828 (1984).
Article  ADS  Google Scholar 
Hisamoto, D., Kaga, T., Kawamoto, Y. & Takeda, E. A fully depleted lean-channel transistor (DELTA): a novel vertical ultra thin SOI MOSFET. Tech. Digest IEEE Electron Devices Meet. 833–836 (IEEE, 1989). The DELTA transistor was the first multigate transistor, and dynamic random access memory cells based on DELTA devices were reported two years later.
Google Scholar 
Huang, X. et al. Sub 50-nm FinFET: PMOS. Tech. Digest IEEE Electron Devices Meet. 67–70 (IEEE, 1999).
Google Scholar 
Baie, X., Colinge, J. P., Bayot, V. & Grivei, E. Quantum-wire effects in thin and narrow SOI MOSFETs. IEEE Int. SOI Conf. Proc. 66–67 (IEEE, 1995).
Google Scholar 
Doyle, B. S. et al. High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Device Lett. 24, 263–265 (2003).
Article  CAS  ADS  Google Scholar 
Park, J. T., Colinge, J. P. & Diaz, C. H. Pi-gate SOI MOSFET. IEEE Electron Device Lett. 22, 405–406 (2001).
Article  ADS  Google Scholar 
Yang, F. L. et al. 25 nm CMOS omega FETs. Tech. Digest IEEE Electron Devices Meet. 255–258 (IEEE, 2002).
Book  Google Scholar 
Colinge, J. P., Gao, M. H., Romano, A., Maes, H. & Claeys C. Silicon-on-insulator ‘gate-all-around device’. Tech. Digest IEEE Electron Devices Meet. 595–598 (IEEE, 1990).
Book  Google Scholar 
Colinge, J. P. et al. Nanowire transistors without junctions. Nature Nanotechnol. 5, 225–229 (2010).
Article  CAS  ADS  Google Scholar 
Ansari, L., Feldman, B., Fagas, G., Colinge, J. P. & Greer, J. C. Simulation of junctionless Si nanowire transistors with 3 nm gate length. Appl. Phys. Lett. 97, 062105 (2010).
Article  ADS  Google Scholar 
Hofmann, F. et al. NVM based on FinFET device structures. Solid State Electron. 49, 1799–1804 (2005).
Article  CAS  ADS  Google Scholar 
Tang, X. et al. Self-aligned SOI nano flash memory device. Solid State Electron. 44, 2259–2264 (2000).
Article  CAS  ADS  Google Scholar 
Suk, S. D. et al. Characteristics of sub 5nm tri-gate nanowire MOSFETs with single and poly Si channels in SOI structure. Symp. VLSI Technol. 142–143 (IEEE, 2009).
Google Scholar 
Park, J. T., Colinge, C. A. & Colinge, J. P. Comparison of gate structures for short-channel SOI MOSFETs. IEEE Int. SOI Conf. 115–116 (IEEE, 2001).
Google Scholar 
Kuhn, K. J. CMOS transistor scaling past 32nm and implications on variation. IEEE/SEMI Advanced Semicond. Manuf. Conf. 241–246 (IEEE, 2010).
Google Scholar 
Okano, K. et al. Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10nm fin width and 20nm gate length. Tech. Digest IEEE Electron Devices Meet. 725–728 (IEEE, 2005).
Google Scholar 
Cho, H. J. et al. Fin width scaling criteria of body-tied FinFET in sub-50 nm regime. Conf. Digest Device Res. Conf. 209–210 (IEEE, 2004).
Google Scholar 
Kanemura, T., Izumida, T., Aoki, N. & Kondo, M. Improvement of drive current in bulk-FinFET using full 3D process/device simulations. Int. Conf. Simulation Semicond. Processes Devices 131–134 (IEEE, 2006).
Google Scholar 
Cao, S., Chun, J. H., Salman, A. A., Beebe, S. G. & Dutton, R. W. Gate-controlled field-effect diodes and silicon-controlled rectifier for charged-device model ESD protection in advanced SOI technology. Microelectron. Reliab. 51, 756–764 (2011).
Article  CAS  Google Scholar 
Thijs, S. et al. Advanced ESD power clamp design for SOI FinFET CMOS technology. Int. Conf. IC Design Technol. 43–46 (IEEE, 2010).
Google Scholar 
Subramanian, V. et al. Planar bulk MOSFETs versus FinFETs: an analog/RF perspective. IEEE Trans. Electron Devices 12, 3071–3079 (2006).
Article  ADS  Google Scholar 
Yan, R. H., Ourmazd, A. & Lee, K. F. Scaling the Si MOSFET: from bulk to SOI to bulk. IEEE Trans. Electron Devices 39, 1704–1710 (1992).
Article  CAS  ADS  Google Scholar 
Lee, C. W. et al. Device design guidelines for nano-scale MuGFETs. Solid State Electron. 51, 505–510 (2007).
Article  CAS  ADS  Google Scholar 
Colinge, J. P. in FinFETs and Other Multi-Gate Transistors (ed. Colinge, J. P.) 1–48 (Springer, 2007).
Google Scholar 
Kavalieros, J. et al. Tri-gate transistor architecture with high-κ gate dielectrics, metal gates and strain engineering. Digest Tech. Papers Symp. VLSI Technol. 50–51 (IEEE, 2006).
Google Scholar 
Yeh, C.-C. et al. A low operating power FinFET transistor module featuring scaled gate stack and strain engineering for 32/28nm SoC technology. IEEE Electron Devices Meet. 772–775 (IEEE, 2011).
Google Scholar 
Joshi, R. V. et al. FinFET SRAM for high-performance low-power applications. Proc. 34th Eur. Solid-State Device Res. Conf. 69–72 (IEEE, 2004).
Google Scholar 
Basker, V. et al. A 0.063 μm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch. Symp. VLSI Technol. 19–20 (IEEE, 2010).
Google Scholar 
Guillorn, M. A. et al. A 0.021 μm2 trigate SRAM cell with aggressively scaled gate and contact pitch. Symp. VLSI Technol. 64–65 (IEEE, 2011).
Google Scholar 
Wu, C. C. et al. High performance 22/20nm FinFET CMOS devices with advanced high-K/metal gate scheme. IEEE Electron Devices Meet. 600–603 (IEEE, 2011).
Google Scholar 
ITRS International Technology Working Groups. ITRS 2010 update. International Road Map for Semiconductorshttp://www.itrs.net/Links/2010ITRS/2010Update/ToPost/2010Tables_ORTC_ITRS.xls〉 (2010).
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This work was supported by Science Foundation Ireland grants 05/IN/I888, 07/IN.1/I937 and 10/IN.1/I2992, the European project SQWIRE under Grant Agreement No. 257111 and the European Community (EC) Seventh Framework Program through the Network of Excellence Nano-TEC under Contract 257964. We thank N. Petkov and M. Schmidt for the electron microscopy images in Fig. 6.
Tyndall National Institute, University College Cork, Lee Maltings, Dyke Parade, Cork, Ireland
Isabelle Ferain, Cynthia A. Colinge & Jean-Pierre Colinge
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Correspondence to Jean-Pierre Colinge.
The authors declare no competing financial interests.
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Ferain, I., Colinge, C. & Colinge, JP. Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors. Nature 479, 310–316 (2011). https://doi.org/10.1038/nature10676
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