Mirabilis Design tại Hội nghị Tự động hóa Thiết kế 2024
This is the first time in 28 years of my visits to DAC that I have seen so many different technologies arrive at DAC in the same year. Earlier we would have one or possibly two innovative breakthroughs in semiconductors and embedded systems that emerged at DAC. This year I expect six or may be seven to arrive, and I am not including the innovations in EDA software.
At the system-level, new architectures are propelling the need for a shift-left methodology that integrates system-level analysis and exploration, architecture trade-offs, communication with partners and requirements monitoring. Trending technologies include multi-die and Chiplets, RISC-V and ARM co-habiting, power and thermal challenges leading to more complex power management architectures, AI engines vs. GPU for vector and convolution, common architecture for all EV automobiles, micro-assurance experiments, and latency analysis of analog systems.
In the post-Covid era, Mirabilis Design has recognized the emergence of these trends. To support these trends, we have introduced the concept of validated system-level IP and capabilities on top of performance models. System-level IP blocks to support Chiplets/UCIe, PCIe6.0, LPDDR_5X, DDR5, DSP, GPU, AI Engines, NoCs, and DSP have been added to the flagship VisualSim Architect. Requirements can be imported from a variety of database and is fully integrated with the simulator, that provides continuous monitoring. Other new features include thermal characteristics from the power modeling of a cycle-accurate performance model, AI workloads such as DNN partitioning on to AI/GPU/CPU, failures modeling and generation of UPF/UVM/SystemVerilog files for early verification.
We are witnessing a spurt in interest by semiconductor and automotive design communities in exploring the revamped version of VisualSim. We strongly believe this trend will expand further as more and more designs require AI engines and devices becoming power hungry leading to an increase in thermal cost.
Chiplets have been recognized as the right choice of solution as a rapid response to new customer requirements. Building a stock/base of different configurations that can be easily assembled for a new application is essential. The VisualSim model of the application architecture enables a new market for chiplet IP vendors and semiconductor companies. Both can collaborate to create a solution that is optimized for the target application and workload to meet the Power-Performance-Area. VisualSim hardware builders have been proven to create a new generation of SoC in about 2 weeks, thus enabling rapid trade-off, and dynamic documentation for distribution to OEMs and suppliers.
Power has become extremely important in both traditional processors and emerging applications such as AI, GPU, automotive architecture. VisualSim Power Digital Twin has been built on top of the VisualSim performance model. The design can incorporate power management, large number of states, dynamic and leakage, distribution and attenuation, negative impact of power management, batteries, and power generators such as solar panels. The models provides instantaneous and average power plots, power improvement for a new power management architecture, output thermal characteristics for temperature and heat, power for workloads and individual IP and generate SystemVerilog test benches and UPF files.
Inspite of the fact that the large vendors of the EDA industry are missing, I believe it will still be an important one for both the electronics engineers and the EDA companies supporting them.
Website: https://www.mirabilisdesign.com
Also Read:
A Modeling, Simulation, Exploration and Collaborative Platform to Develop Electronics and SoCs
Mapping SysML to Hardware Architecture
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