Đồng tối ưu hóa Kiến trúc CTNH, Dấu chân bộ nhớ, Vị trí thiết bị và Lập kế hoạch vận hành trên mỗi chip (Georgia Tech, Microsoft)

A technical paper titled “Integrated Hardware Architecture and Device Placement Search” was published by researchers at Georgia Institute of Technology and Microsoft Research.

Abstract:

“Distributed execution of deep learning training involves a dynamic interplay between hardware accelerator architecture and device placement strategy. This is the first work to explore the co-optimization of determining the optimal architecture and device placement strategy through novel algorithms, improving the balance of computational resources, memory usage, and data distribution. Our architecture search leverages tensor and vector units, determining their quantity and dimensionality, and on-chip and off-chip memory configurations. It also determines the microbatch size and decides whether to recompute or stash activations, balancing the memory footprint of training and storage size. For each explored architecture configuration, we use an Integer Linear Program (ILP) to find the optimal schedule for executing operators on the accelerator. The ILP results then integrate with a dynamic programming solution to identify the most effective device placement strategy, combining data, pipeline, and tensor model parallelism across multiple accelerators. Our approach achieves higher throughput on large language models compared to the state-of-the-art TPUv4 and the Spotlight accelerator search framework. The entire source code of PHAZE is available at this https URL.”

Find the technical paper here. Published July 2024 (preprint).

Wang, Irene, Jakub Tarnawski, Amar Phanishayee, and Divya Mahajan. “Integrated Hardware Architecture and Device Placement Search.” arXiv preprint arXiv:2407.13143 (2024).

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