Codasip tại Hội nghị tự động hóa thiết kế 2924
Codasip will be demonstrating it’s new L110 core alongside Codasip Studio Fusion at #61DAC. Codasip L110 delivers up to 50% improvements in performance per watt and 20% smaller code size compared to similar cores in the market. The core offers extensive configurability, allowing different area/performance trade-off levels, and support for standard RISC V code-size extensions. Additionally, the L110 is fully customizable allowing designers to extend the processor to achieve massive PPA improvements to differentiate their products. Designed by the Codasip team using Codasip Studio Fusion, L110 is ideal for small-area, low-power applications, such as state machine replacements, sensor controllers, and IoT edge.
Codasip Studio has been the toolset to generate both the RTL and the software development tools from one processor model for years. The latest version, Codasip Studio Fusion, improves this fundamental capability and adds a layer of segmentation. You can configure the core from set options, create custom instructions within set bounds, or design freely.
Codasip will be showcasing both of these new products at the 2024 DAC show through the, Anomaly Detection in Near-Sensor Embedded Devices Demo. Which enables for AI/DSP on Tiny Processors optimized through Bounded Customization.
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