Cadence vẽ một bức tranh rộng lớn về ô tô

Cadence recently launched a webinar series on trends and challenges in automotive design. They contribute through IP from their Silicon Solutions Group, a comprehensive spectrum of design tooling and through collaborative development within a wide partner ecosystem. This collaboration aims to support and advance progress through reference architectures and platforms co-developed with auto OEMs, AI solution builders, foundries and others. I’m writing here on the overview webinar. Check-in with Cadence on upcoming webinars in the series which will dive more deeply into these topics.

Market trends

Automotive options today can be overwhelming: BEVs versus HEVs, ADAS versus different flavors of autonomous driving, in-cabin features galore, often at eye-popping prices. No wonder auto OEMs are juggling architectures, production priorities and radical ideas to monetize mobility. Yet all this churn also represents expanding opportunities in the supply chain, for Tier1s, semiconductor suppliers, foundries, and beyond. Automotive semiconductors are expected to deliver a CAGR of 11% through 2029 and the silicon carbide market (critical to support EV trends) is expected to grow even faster, at a CAGR or 24% through the same period.

Growth is driven in part by electrification and in part by increased sensing and AI content to add more intelligence to ADAS, autonomous driving (AD) and the driver/passenger safety and experience. All this new capability adds cost in hardware, creating pressure tο mitigate costs by consolidating electronics content into a smaller number of devices through zonal architectures. It also adds complexity in software/AI modeling, further contributing to cost and amplifying safety concerns through disaggregated software and AI model development and support, in turn pushing for more vertical integration in the supply chain.

Robert Schweiger (Group Director, Automotive Solutions at Cadence) observed that, as a key supplier in this design chain, Cadence sees a clear trend to vertical integration among auto OEMs and Tier1s now wanting to be hands-on in critical semiconductor and systems design. This isn’t necessarily bad news for automotive semiconductor companies; they too will participate but markets for advanced systems are becoming more competitive.

Robert recapped some sensor trends from this year’s AutoSens conference, some of which I have talked about elsewhere but I think are worth repeating here. Hi-res (8MP) cameras will become mainstream in support of AI. Low-cost, “unintelligent” cameras will also play a role in transferring raw video streams to the central processor on which AI-based inferences can be overlaid. 4D imaging radar (4DR) is catching up fast versus Lidar (except so far in China) thanks to lower pricing. In-cabin sensing for driver monitoring systems (attention, alertness) is now a requirement for a top safety rating according to the EURO-NCAP standard. Similarly, occupancy detection (did I leave a child in the backseat when I locked the car?) is becoming more popular. Both systems use in-cabin cameras or radar.

Cadence automotive technology update

In interest of brevity here I will just call out recent updates. The Tensilica group has been very active, introducing new vision cores (3xx series) and a 4DR hardware accelerator that can be used for vision and radar applications, to which you can add a Neo (or other) NPU for higher-performance AI tasks. I found a zonal controller graphic very interesting here, a single controller connecting to multiple radar and vision sensors, processing vision and radar streams before handing off to a fusion accelerator for enhanced point cloud generation. Clearly, the zonal controller must be close enough to the sensors with a high-speed link  to manage bandwidth/latency between sensors and that controller.

On connectivity, Robert anticipates Automotive Ethernet will play a big role between central and zonal ECUs. At the edges between sensors and zonal ECUs, options are not yet quite so standardized, trending to SERDES-based interfaces to provide necessary bandwidth or MIPI in cases that aren’t quite as demanding. Cadence SSG has connectivity solutions to support all these options.

3D-IC is another important objective in total system cost reduction. Notable recent additions here are Integrity 3D-IC to guide planning, co-design, cross-die optimization, Allegro for package layout co-design and Virtuoso with 3D analysis. Together with UCIe controller, PHY, and verification IP.

In verification, there has been a variety of Verification IP updates. The Helium platform plus integration with Palladium and Protium platforms enables a hybrid virtual prototyping design flows allowing for software development in the cloud as hardware is under development. The MIDAS safety platform drives verification of safety requirements through the Unified Safety Format (USF) with both digital and analog design to ensure compliance with ISO 26262/ASIL requirements. Also now Palladium emulation platforms are fault-simulation-capable, making full-SoC analyses with software stacks practical for system-level safety validation.

In system design and analysis I didn’t see recent updates but of course Cadence hosts a full suite of thermal, RF, EM, SI/PI and CFD solutions, applicable from chip, to board, to rack, even to datacenter.

Finally, Robert also introduced a new Power Module Flow for the design of silicon carbide-based power electronic systems for advanced EV powertrain applications. This flow targets power module design considering thermal, EMI and mechanical stress factors plus die and package co-optimization.

Partnerships / collaborative development

Getting to convergence in this massive re-imagination of a modern car is only possible through major collaborations, prototyping, building reference designs, and integrating with cloud-native software development platforms.

One example is the ZuKiMo government-funded project, taped out on GF22nm and demoed at Embedded World 2024, featuring DreamChip’s latest automotive SoC, hosting Automotive Ethernet, Tensilica AI accelerator IP, and BMW AI image recognition.

At Chiplet Summit 2024 Cadence demonstrated a 7-chiplet system connected through their UCIe in a standard package, running at up to 16GT/s.

Cadence is also collaborating with Arm in support of the SOAFEE initiative, supporting cloud-native design starting with Helium-based virtual prototyping, while allowing subsystems to progressively transition to hardware-based modeling for more precise validation as a design stabilizes.

As one last telling example of collaboration, Tesla has partnered with Cadence to develop their DOJO AI platform, their next step in a full self-driving solution.

In summary, Cadence is plugged into automotive whichever way markets go. You can sign up for the next webinar in the series HERE.

Also Read:

Analog IC Migration using AI

The Next LLM Architecture? Innovation in Verification

Emerging Growth Opportunity for Women in AI

Addressing Reliability and Safety of Power Modules for Electric Vehicles

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