Arteris đang giải quyết các thách thức tích hợp SoC
The difficulty of SoC integration is clearly getting more demanding. Driven by process node density, multi-chip integration and seemingly never-ending demands for more performance at lower power, the hurdles continue to increase. When you consider these challenges in the context of Arteris, it’s natural to think about hardware integration and the benefits a network-on-chip (NoC) technology offers. But the problem is much bigger than hardware integration and so is the portfolio of solutions offered by Arteris. Managing all the information associated with a complex design and ensuring all teams are working off the same verified information is a daunting task. What you don’t know can hurt you. I recently had the opportunity to learn about the broader solution Arteris offers. Read on to see how Arteris is solving SoC integration challenges.
An Overview of the Problem
While most folks immediately think “NoC” when they hear Arteris, the company is assembling a much broader portfolio of solutions. The common thread is that they all facilitate more efficient and predictable connectivity and assembly of the design. At the highest level, the way I think about the company’s role is this – focus on your unique design idea and let Arteris help you put it all together.
I was able to spend some time recently with Insaf Meliane, Product Management & Marketing Manager at Arteris. Insaf has been with Arteris for three years. She came to Arteris through the company’s acquisition of Magillem, where she worked for four years prior to joining Arteris. She has a rich background in chip design from places such as NXP Semiconductors, ST Microelectronics and ST-Ericsson. Insaf was able to enlighten me about how Magillem’s technology helps Arteris deliver a holistic solution to the SoC integration problem. She began by describing the problem.
The information Insaf shared was, in part, based on actual customer discussions. She described SoC integration as a massive amount of hardware and software information each design creates and how that data interacts with the design flow and all the teams using it.
She described current designs that can contain 500+ up to 1K IP blocks with 200K+ up to 5M+ registers. She pointed out that the management of this sea of IP blocks is getting more critical to ensure a successful project. Specific challenges include:
- Content integration from various sources (soft IP, configurable 3rd party IP, internal legacy…)
- Design manipulation (derivative, repartitioning, restructuring)
Against this backdrop, traditional design methodologies with homegrown solutions are reaching their limits and there is significant manual effort across a large variety of design tasks. She explained that many different forms of design information exist. For example, spreadsheets, Docx, IP-XACT, and SystemRDL to name a few.
This results in limited cross-team synergy. Miscommunication can lead to specification misalignment, which can cause huge problems in the form of late fixes or even re-spins if issues cannot be resolved in software. Management of all this information in a coherent, reliable way can deliver the margin of victory for a complex design project.
The Arteris Approach with Magillem
Insaf described a typical design project where one team uses register documentation, another team uses a verification environment, a third is turning a netlist into a layout and a fourth is developing the primary architecture with top RTL. The question is, how can you find all inconsistencies in each of these (independent) sources of information and what are the consequences of missing something?
Deploying a single source of truth for the myriad of design information is the answer, and the path to a better design. It turns out IP-XACT offers an industry standard, proven data model. It supports systematic IP reuse and IP interoperability and facilitates IP packaging for efficient handling of all aspects of system integration such as connectivity, configurability and the hardware/software interface. It also offers a solid API to access all design data with a powerful scripting environment.
As a major Contributing Member of the Spirit/Accellera Consortium (driving IP-XACT standards since inception & Co-chair of the IP-XACT 2021 Accellera committee), Arteris has proven experience with IP-XACT usage. The figure below summarizes the benefits of the approach.
This approach delivers a unified environment that can be used by all teams to maximize collaborative work and data accuracy. It allows for the development of a vendor-independent flow and facilitates portability of the design environment to third parties, partners, and customers.
This is the architecture of the Magillem products from Arteris, and it delivers constant repeatability for design derivatives, projects, and design flows. The result is higher productivity and quality with a consistent end-to-end design flow solution. Insaf elaborated on the many capabilities delivered by the Magillem tool. A link is coming so you can dig deeper, but here is a summary list:
For connectivity
- Project Management: Design navigation and data aggregation
- Parameters Configuration: Hierarchical propagation or overriding
- SoC Assembly: Bus i/f detection, rule-based connectivity, bus/signal split/tie/open, hierarchical connection, glue logic insertion, feedthrough
- Hierarchy Manipulations: Move, merge, and flatten a physical/virtual hierarchy for RTL restructuring/partitioning
- Platform Derivatives: With the incremental design, automatic update, and design diff and merge capability
- Comprehensive Checkers: Catch errors as you enter the design information before running any simulation
- Advanced Generation Capability: RTL Netlist generation, connectivity report in addition to makefile scripts for an extensive range of EDA tools
- Tool Integration: Tight link with the Registers tool to generate a system address map when both tools are combined
For registers and memory map
- Single Database: Import and capture memory map information into a single database (IP-XACT)
- Parameterization: including configurable properties, custom specific access types and register modes
- Comprehensive Checkers: Catch errors early in the process with built-in and custom checkers
- Standard Formats Support: Output standard formats for HW design and verification, embedded SW, and documentation
- Custom Templates: Advanced generation capability with support for custom template-based generators
- Merge/Flatten IP Memory: Enable easy update/manipulation/creation of new global memory map for a sub-system or SoC
Insaf spent some time on the restructuring capabilities offered by Magillem. This is a very powerful capability to address power and floor-planning constraints. Features include:
- Automated hierarchy manipulation from the connectivity tool
- Separating RTL hierarchy and physical hierarchy
- Feedthrough connections for abutted floorplan
- Hard macros replication
There are many uses for RTL restructuring, including:
- to adapt to new design changes
- to create design derivatives
- to optimize the netlist for physical design
- to improve the overall congestion of the design
- to meet SoC’s power and floor-planning constraints
- to disaggregate the SoC into chiplets for multi-die designs
She explained these capabilities can reduce design time from weeks to 1-2 days. Indeed the tool automatically updates the design connections after restructuring, enabling quick and safe adaptation before delivering a formally equivalent RTL netlist to the physical design team.
The figure below provides a broad overview of all the capabilities Arteris delivers for SoC integration along with the standards and EDA tools that are supported.
A high-level summary of these capabilities includes:
- Connectivity:
- IP packaging
- Design assembly
- Registers:
- Memory map intent capture
- Hardware/software interface generation
- Suite combining connectivity and registers: system map validation
To Learn More
I’ve only touched on the basics here. The capabilities offered by Arteris to effectively manage and integrate the information associated with a complex design is substantial. You can learn more about Magillem’s connectivity capabilities here and Magillem’s register management capabilities here. You can also contact Arteris to discuss your specific requirements. And that’s how Arteris is solving SoC integration challenges.
Share this post via:
