Định tuyến dữ liệu trong thiết kế chip không đồng nhất

Ensuring data gets to where it’s supposed to go at exactly the right time is a growing challenge for design engineers and architects developing heterogeneous systems. There is more data moving around these chips with dozens of targets, which makes routing signals much more complicated. Ronen Perets, senior product marketing manager at Cadence Design Systems, talks about some of the new problems engineers are likely to encounter with multi-vendor chiplets, what can happen when communication is not consistent, and the impact of multiple communications links between each routing node.