Advanced Packaging Materials for Semiconductor Chips – AZoM
The field of electronics, particularly integrated circuit (IC) technology, has advanced rapidly in recent years. With the development of 5G/6G mobile technology, semiconductor devices are evolving to be smaller, lighter, and more powerful. Packaging is crucial for semiconductor chips, serving roles in physical protection, electrical connection, and adhering to standard specifications. 
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Modern packaging not only protects chips and improves thermal conductivity and reliability but also acts as a link between the chip's internal components and the external circuit. Recent strides in manufacturing and materials science have significantly advanced semiconductor chip and electronics packaging.
Modern semiconductor packaging has progressed significantly. The latest trends in semiconductor packaging have been discussed in a recent article published in IEEE Transactions on Components, Packaging, and Manufacturing Technology.
The semiconductor packaging landscape includes various integration approaches. 2-D IC integration is prevalent, involving at least two chips on the same package substrate or fan-out redistribution layer (RDL) substrate. Systems-in-Package (SiP) is a common 2-D IC integration used in consumer products like smartwatches and smartphones.
The 2.1-D IC integration involves fabricating fine metal layers directly on top of a build-up package substrate or high-density interconnect (HDI). In 2.5-D IC integration, chips are supported by a passive through-silicon via (TSV) interposer, attached to a package substrate—AMD's Radeon R9 Fury X GPU utilizes this technology.
3-D integration encompasses both 3-D IC packaging and 3-D IC integration, stacking chips vertically. The key distinction is the use of TSVs in 3-D IC integration, which is not present in 3-D IC packaging.
Chiplet design and heterogeneous integration packaging have recently gained significant attention.
Prominent examples include Intel's field-programmable gate array (FPGA) like Xilinx/TSMC's Virtex, microprocessors such as AMD's Extreme Performance Yield Computing (EPYC), and Intel's Lakefield, which are in high-volume manufacturing (HVM), utilizing chipset designs and heterogeneous integration packaging.
This innovative approach involves breaking down the System-on-Chip (SoC) into smaller chipsets. These chipsets, which are often diverse in materials and functions, and originate from different fabless design houses, foundries, wafer sizes, feature sizes, and companies, are then integrated using advanced packaging technology.
This enables the creation of a cohesive system or subsystem with enhanced flexibility and performance.
In the context of electrical performance for insulation materials, there is a growing preference for materials with low dissipation factor (Df or loss tangent) and low dielectric constant (Dk or permittivity), especially in the realm of 5G applications.
In scenarios involving multilayer substrates or Redistribution Layers (RDLs), dielectric films (insulating materials) serve as interlayer adhesives between the conductor layers. These materials play a crucial role in maintaining the integrity and efficiency of electronic components.
In the post-Moore era, the significance of advanced packaging has intensified to address the enduring requirements of electronic products, encompassing smaller sizes, enhanced performance, and reduced cost.
As per the article published in Fundamental Research, there has been rigorous development in advanced packaging, such as TSMC's InFO (integrated fan-out) and CoWoS (chip on wafer on substrate), ASE's FOCoS (fan-out chip on substrate), as well as Amkor's SLIM (siliconless integrated module) and SWIFT (silicon wafer integrated fan-out technology).
These advancements aim to push the boundaries of electronic packaging capabilities.
There are several challenges faced by TSV-based 3D packaging technology. Yield poses a significant challenge in 3D stacking, especially when integrating multiple chips. The failure of a single chip during manufacturing can fail the entire module.
The bonding methods employed for 3D IC integration demand stringent conditions, including high surface cleanliness, surface flatness, and cleanroom class. Additionally, effective thermal management becomes a challenge in 3D packaging due to the high packaging density, requiring innovative solutions to address these complexities.
Approximately 90 % of Integrated Circuits (ICs) are enclosed in plastic electronic packaging using underfill materials that consist of an epoxy matrix and high levels of silica with a low coefficient of thermal expansion (CTE).
However, the existing epoxy-based underfill materials (EUMs) commercially available have a low thermal conductivity of only 0.4 W/m⋅K. This thermal conductivity falls short of meeting the rigorous heat transfer requirements for the next generation of high-power electronic devices.
Enhancing the thermal conductivity of epoxy composites is not the sole factor to ensure their practical application as EUMs. Other processing considerations and the demands of electronic devices in service must also be considered.
For instance, liquid epoxy-based encapsulants should exhibit favorable fluidity at room temperature, allowing them to effectively fill spaces during capillary flow processes in completed Integrated Circuits (ICs).
According to the article published in Composites Science and Technology, strategies aimed at optimizing the thermal conductivity of EUMs without compromising factors such as processability, electronic insulation, Coefficient of Thermal Expansion (CTE), and mechanical properties are currently attracting significant attention but remain challenging.
The researchers conducted experiments to demonstrate that incorporating small quantities (0.5 vol %) of silver nanowires (AgNWs) into EP/S-Al2O3 composites significantly increased thermal conductivity without compromising processability.
The rigid nanowires bridged the main spherical particles, resulting in a 106.5 % increase in thermal conductivity in the micro nano EP/AgNWs/S-Al2O3 composites with 40 vol % S-Al2O3 and 0.5 vol % AgNWs, compared to those without AgNWs.
These findings suggest that incorporating multiscale fillers into epoxy composites can address the tradeoff between thermal conductivity and processability, making them suitable for applications in high-power-density electronic devices.
Power chips used in high-tech equipment generate significant heat. However, the absence of micro-cooling technology results in elevated chip temperatures, leading to reduced lifespan, diminished capabilities, and lower reliability. Research to enhance chip cooling primarily centers on two approaches.
The first involves creating efficient micro-scale heat dissipation mechanisms, such as advanced heat sinks. The second concentrates on developing high-performance thermal management materials, optimizing overall chip cooling.
The latest article in Micro-machines has highlighted that metal matrix composites (MMCs) composed of a matrix metal with high thermal conductivity (TC) and reinforcing phases show significant potential for development. SiC/Al composite materials possess exceptional properties, including high specific strength, high specific modulus, elevated hardness, wear resistance, good thermal stability, and strong fatigue strength.
Their manufacturability using conventional methods makes them highly promising for applications in electronic packaging materials.
Building on the success of SiC/Al electronic packaging materials, there is a growing interest in SiC-based composites featuring a Cu matrix (SiC/Cu). Leveraging microfabrication techniques, SiC/Cu composites are emerging as prime contenders for the next wave of electronic packaging materials.
These composites are particularly sought after for high-performance heat dissipation devices and electronic packaging applications, thanks to their high thermal conductivity (TC) and low coefficient of thermal expansion (CTE).
The trend toward higher packaging density and thinner chips in chip manufacturing processes introduces increased sensitivity to stress, contaminants, and inconsistencies. Addressing these challenges requires the development of new techniques, including low-cost high-performance bonding and large-scale metrology with high precision.
These advancements are crucial to tackle manufacturing issues such as yield and reliability. Advanced packaging emerges as a promising solution to maximize the advantages of scaling down by exploring new architectures, reducing communication distances, and achieving higher packaging density.
To realize these goals, standardization, the adoption of new techniques, co-design tools, and multi-scale multi-physics simulation techniques are essential for the sustainable development of advanced packaging technology.
More from AZoM: What is the Role of the Depletion Region in a Semiconductor PN Junction?
MoreSuperHard. (2023). The Key Materials Used for Semiconductor Advanced Packaging and Testing. [Online] MoreSuperHard. Available at: https://www.morediamondwheel.com/blog/the-key-materials-for-semiconductor-advanced-packaging/ (Accessed 11 February 2024).
Lau, JH. (2022). Recent advances and trends in advanced packaging. IEEE Transactions on Components, Packaging and Manufacturing Technology. doi.org/10.1109/TCPMT.2022.3144461.
Chen, Z., et al. (2023). Challenges and prospects for advanced packaging. Fundamental Research. doi.org/10.1016/j.fmre.2023.04.014.
Hu, Y., et al. (2021). Novel micro-nano epoxy composites for electronic packaging application: Balance of thermal conductivity and processability. Composites Science and Technology. doi.org/10.1016/j.compscitech.2021.108760.
Lai L., et al. (2023). Advancements in SiC-Reinforced Metal Matrix Composites for High-Performance Electronic Packaging: A Review of Thermo-Mechanical Properties and Future Trends. Micromachines. doi.org/10.3390/mi14081491.
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Ibtisam graduated from the Institute of Space Technology, Islamabad with a B.S. in Aerospace Engineering. During his academic career, he has worked on several research projects and has successfully managed several co-curricular events such as the International World Space Week and the International Conference on Aerospace Engineering. Having won an English prose competition during his undergraduate degree, Ibtisam has always been keenly interested in research, writing, and editing. Soon after his graduation, he joined AzoNetwork as a freelancer to sharpen his skills. Ibtisam loves to travel, especially visiting the countryside. He has always been a sports fan and loves to watch tennis, soccer, and cricket. Born in Pakistan, Ibtisam one day hopes to travel all over the world.
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