Đánh giá blog: ngày 10 tháng 7
Mixed-signal verification; 3D-IC physical verification; soft chiplets; heterogenous compute in cars.
Cadence’s Paul Graykowski suggests using real number modeling to streamline digital mixed-signal verification using logic simulators and hardware emulators.
Siemens’ John McMillan and Microsoft’s Amit Kumar introduce the basics of 3D-IC, describe the flow and data management challenges, look at the evolution of TSMC 3DBlox 1.0 and 2.0, and detail a physical verification and reliability analysis flow for 3D-IC.
Synopsys’ Manmeet Walia, Manuel Mota, and Erez Shaizaf find that customizable soft chiplets that users can harden for a specified process node and package while retaining the benefits of design flexibility and architecture optimization.
Arm’s Suraj Gajendra notes that key automotive use cases, like ADAS, autonomous driving, and in-vehicle infotainment, require a heterogenous compute approach to fulfil their complex computing requirements and highlights efforts to encourage industry-wide collaboration and standardization on chiplets.
Keysight’s Hwee Yng Yeo explains how to use frequency demodulation, a method that can help automotive radar developers effectively extract information from a radar signal for characterizing its performance.
Ansys’ Thierry Marchal checks out how structural and fluid simulation help with the development of single-use bioreactor equipment used in the production of biopharmaceuticals.
SEMI’s James Amano and Ben Kallen consider the use of per- and polyfluoroalkyl substances (PFAS) in semiconductor manufacturing and the potential impact of regulatory proposals.
Plus, check out the blogs featured in the latest Systems & Design, Automotive, Security & Pervasive Computing, and Test, Measurement & Analytics newsletters:
Technology Editor Brian Bailey argues that there must be considerable gain for an innovation to gain traction, or it will just be an interesting idea.
Axiomise’s Nicky Khodadad and Ashish Darbari assess all possible firings of an instruction, along with those before and after.
Cadence’s Anika Sunda delves into the impact of AI/ML and how they are reshaping approaches to design and verification in electronics.
Keysight’s Jonathon Wright discusses how testers’ critical thinking abilities are necessary to balance the mathematical needs of software development with the complex, nuanced needs of the world it seeks to help.
Arteris’ Andy Nightingale shows why an emphasis on physical awareness significantly reduces the iterative cycles of NoC placement and routing.
Synopsys’ Kenneth Larsen explains the differences between 2.5D and 3D IC design approaches, and their unique challenges and benefits.
Siemens’ Jacob Wiltgen digs into challenges in virtualization, model delivery, and traceability.
TXOne’s Yenting Lee explains how an attacker could exploit the weaknesses of SECS/GEM to disrupt process control or inhibit response functions.
Infineon’s Tammie Bard shows how to determine the power loss for sustained output current, and whether a cooling solution is needed.
Cadence’s Reela Samuel examines new complexities, such as die-to-die interconnect standards and the integration of diverse IPs.
Renesas’ David Renno, David Armour, Melissa Hu, and Sezgi Koukourakis look at the low-power benefits of BLE and NFC.
Rambus’ Scott Best warns that AI silicon has an expanded threat surface compared to other systems.
NI’s Juan Valdivia explains why the testing requirements for mixed signal and RF devices are becoming increasingly complex as industries evolve.
Synopsys’ Guy Cortez and Mark Laird dig into the miscorrelation between predicted and actual silicon behavior, including issues when chips run too fast or too slow.
Advantest’s Toni Dirscherl outlines the challenges of testing an evolving list of auto devices, including DRAM, flash memory, MPUs, display drivers, and power devices.
Jesse Allen
Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.
